The headline version of CPO is short: the optical engine moves onto the same substrate as the switch ASIC; the pluggable module disappears; everyone who sells EML laser chips, DSP chips, cages, and faceplate optics has a worse 2028. The headline version is correct, and it’s also useless for understanding why CPO keeps slipping.
The real story is a manufacturing problem. NVIDIA’s next-generation Rubin Ultra rack needs CPO — with 576 GPUs and 115.2 T of interconnect bandwidth per rack, pluggable optics physically cannot keep up. So TSMC is doing the packaging, NVIDIA has prepaid the supply, and as of May 2026 the package’s yield is ~75% against a break-even target of 90–95%. Every quarter the gap closes a few points slower than the prior plan said it would.
This piece is the inside of that gap: what’s actually inside the package, the six steps to assemble it, where each step is losing yield, and who’s positioned around the bottleneck. Companion pieces in the cluster: What AI Hardware Is Running Out Of, What’s Cooling the AI Build-Out, Where Marvell Sits, Where Broadcom Sits. For high-signal official / lab video (NVIDIA + Broadcom CPO first): TPU & CPO YouTube shelf.
What's actually being packaged — the optical engine
The thing called an “optical engine” (OE) is not a single chip. It’s a tightly integrated stack of three layers, every one of which carries a yield risk.
- The chips. A PIC (photonic integrated circuit) is the optical substrate — the circuit that emits, modulates, and receives light. It’s silicon photonics, typically on a 65 nm process. Bonded to it is the EIC (electronic integrated circuit), which drives the lasers and amplifies the received signal: TIA (transimpedance amplifier), driver, and modulator (micro-ring or Mach–Zehnder). The EIC sits at the leading edge — 6 nm or lower.
- The optical glue. The FAU (fibre-array unit) holds the multi-fibre array that physically couples to the PIC’s waveguides. For CPO it’s a three-dimensional design with channel pitch under 100 µm, demanding sub-micron alignment precision — orders of magnitude tighter than the 2-D FAUs used in pluggable modules. Microlenses condition the beam between fibre and PIC. The CW (continuous-wave) laser source sits outside the package, feeding light in over fibre at ≥ 300 mW per channel.
- The plumbing. Optical isolators (to keep reflected light from killing the laser), polarisation-maintaining fibre, and a shuffle box that handles the complex port-to-fibre mapping. Cheap individually; collectively, the integration is what makes the package painful.
The CW source — the “light supply” outside the package — is also where the supply concentrates: Lumentum dominates the ≥300 mW high-power CW laser market, with Coherent the only credible second. That’s a separate bottleneck. See the scarcity map.
The six steps — and where the yield breaks
Step 1 — PIC + EIC hybrid bonding. At the wafer level, the PIC and EIC are aligned face-to-face and hybrid-bonded with sub-micron precision. This is the hardest step in the entire flow and the largest single yield loss — ~10% of CPO units die here. The dedicated coupling / alignment equipment is sold by a small list of vendors (ROR / Robotechnik is the most named); units run $1–2 M with 5–7 month lead times. Two industries’ manufacturing tolerances meet here for the first time, and one of them isn’t used to losing.
Step 2 — wafer dicing. Cut the bonded PIC + EIC wafer into individual optical-engine die. Standard process; small yield impact.
Step 3 — substrate flip-chip. Mount the OE die onto an ABF (Ajinomoto Build-up Film) IC substrate. Standard advanced-packaging plumbing; well understood; the yield here is fine.
Step 4 — FAU active coupling. The second-biggest yield-loss step. The FAU’s fibres have to be actively aligned to the PIC’s waveguides — alignment tolerance is 0.5–0.6 µm. This is not a robot problem you can buy your way out of: it needs experienced process engineers, and the training cycle for one is over six months. A fully-automated FAU packaging line costs ¥10 M+ ($1.4M+). After coupling, the die runs through burn-in, FT (functional test) and SLT (system-level test), each of which adds yield loss and adds cycle time.
Step 5 — system integration. The packaged OE module gets co-mounted with the switch ASIC on one very large carrier substrate — projected to reach 150 mm × 200 mm, bigger than a phone. This step is done by ASE (and other OSATs in rotation); the OE-and-ASIC carrier is the visible “CPO module.”
Step 6 — external CW source attachment. The off-package CW laser is connected via fibre to the CPO module’s FAU mate. TSMC notably abandoned the traditional active-coupling alignment for this connector and went to a blind-mate design — a small, expensive process upgrade that takes a meaningful chunk of cycle time and yield risk out of the end-of-line.
Why yield is stuck at 75%
Three structural reasons, not one.
The DNA mismatch. Semiconductor manufacturing (sub-nanometre, defect-driven yield curves) and optical manufacturing (alignment-driven, hand-tuned, batch-scaled) have never been forced to share a process line at this scale. Where they meet — PIC/EIC bond, FAU coupling — tolerances stack in both domains at once. The compounding is what makes the yield curve hard to flatten.
The thermal problem. The switch ASIC dissipates kilowatts of power. The optical engine sits millimetres away. Light is exquisitely sensitive to temperature: even small drifts walk the laser off-channel, raise the bit-error rate, and force re-tuning. Current liquid cooling (see the cooling map) was designed for the older pluggable thermal envelope; the CPO geometry concentrates heat closer to optics than any liquid stack has had to manage before. Without a step change in the cold-plate design, thermal noise stays a meaningful yield drag.
The test floor. NVIDIA mandates 100% end-to-end test on every wafer — required for reliability at rack-level integration, but brutal for throughput. A wafer holding 200–300 channels takes over twenty hours to fully test. Even with capacity in place, the test floor caps how fast a 90% yield translates to actual rack deliveries.
The combination is why every CPO ramp plan since 2024 has slipped by a quarter. The original 2026 Q2–Q3 ramp is now Q4. The original 2026 volume was a lot bigger than what’s shipping.
The closed NVIDIA – TSMC alliance
The other half of why CPO is hard isn’t technical — it’s ecosystem structure. The reference CPO main line is jointly owned by NVIDIA and TSMC, and the line is not open. External optical-chip vendors, including Broadcom, AMD, and the large pluggable-module makers, are not co-packaging into the same substrate. They are second-tier customers of TSMC’s packaging slots at best, and slot-priority inside TSMC clearly puts NVIDIA above everyone else — particularly when the CPO line is using up yield-limited bonding equipment that Apple, AMD, and Broadcom would also like.
The flip side is CSP resistance. Hyperscalers — Google, AWS, Meta — have three reasons not to adopt CPO quickly:
- Loss of incremental scaling. A pluggable transceiver can be added one port at a time. A CPO rack is a single integrated unit; once it’s designed in, you buy it as a block.
- Pricing power evaporates. The CPO supplier list is essentially one alliance; the pluggable list is dozens. CSP procurement teams don’t like supplier counts of one.
- Ecosystem lock-in. Adopting NVIDIA-TSMC CPO is adopting the whole stack underneath it: the cold plate spec, the rack carrier, the specific switch ASIC family. CSPs that have spent five years building bespoke rack architectures aren’t eager to outsource that to one vendor.
The actual CSP behaviour, as a result, is to wait for NPO (near-packaged optics — the bridge architecture between pluggable and full CPO) and to keep pluggable lines running on the side as insurance. The NPO route is also where Marvell and Broadcom retain a credible socket: SerDes IP under a DSP-less optical engine.
Unit economics
A single CPO switch today carries a sticker price around ¥150,000 versus the comparable electrical switch + pluggable module stack at about ¥80,000. The CPO price holds, but only because no one’s ramped volume yet — full-year 2026 CPO switch shipments are projected at about 15,000 units, based on the 75% yield. That is nowhere near volume-economic, which is part of why TSMC has slow-walked the ramp: a few hundred million dollars of annual revenue against tens of billions on competing leading-edge nodes is not a fight for resources TSMC wants to lose.
Who's where — orders and project status
- NVIDIA. Ordered 20,000 PIC wafers from TSMC in February 2026 to secure supply. The first CPO switches (Rubin-class) are expected to ship August / September 2026, with full-year 2026 shipments in the few-thousand to 15,000 range. To lock in raw optical inputs, NVIDIA placed a $2 B equity investment into Coherent and put a multi-billion-dollar purchase commitment with Lumentum. The original Q2–Q3 2026 ramp is now Q4.
- Broadcom. Behind on every dimension. Its CPO approach is a 2.5-D packaging (vs TSMC’s 3-D), and there is no 2026 volume target on the table. Volume is guided for 2H 2027 → 2028 — not coincidentally, the same window in which Broadcom’s own EML + DSP business has the most to lose. (See the Broadcom catch-22.)
- TFC Communication (天孚通信). NVIDIA’s core optical-component supplier for the OE: FAU, microlens, lens caps, ferrules. Delivered a first 7,200-piece FAU order — demo + verification volume only, not production. Eight CPO lines stood up in Suzhou; target mass-production window Q3–Q4 2026.
- Foxconn Industrial Internet (工业富联). NVIDIA’s exclusive CPO switch assembler. Currently small-batch testing alongside Rubin Super Pod; production-and-delivery window Q4 2026. FY 2027 target 25,000 units, with realistic delivery expected around 10,000+ units given upstream constraints.
- Innolight (中际旭创). Submitted an NPO solution — not CPO — to NVIDIA. Running CPO pre-research with JCET on the side. Effectively: betting on the bridge generation while CPO sorts itself out.
- USI / Universal Scientific (环旭电子). NPO samples in development; mid-2026 mock-up expected. Same bridge-tier bet.
- Coherent (II-VI). Bagged a large CPO solution order from a top AI data-centre customer (effectively NVIDIA-side); CW source sample shipments already running. Coherent’s diamond-particle SiC ceramic thermal- management material (see the scarcity map) sits on the periphery of this story as the one materials piece that doesn’t care which CPO route wins.
The shape
Three stacked truths.
- The demand is real and not optional. Rubin Ultra’s 115.2 T per-rack interconnect is physically beyond pluggable optics. NVIDIA has to ship CPO. So does anyone selling racks above ~600 GPUs.
- The bottleneck is concrete. TSMC’s PIC/EIC hybrid-bond + FAU active-coupling yield is 75%, target 90–95%, and the gap is closed by experienced engineers with six-month training cycles and bonder equipment with six-month lead times. Quarter slips compound.
- The ecosystem is closed and that’s on purpose. NVIDIA + TSMC’s incentives align with shipping their joint CPO main line first; third parties wait. CSPs, also rationally, hedge into NPO and keep pluggables.
Net: real volume on CPO is a 2027–2029 story, with the 2026 number staying inside five digits. The pluggable optical-module empire (EML, DSP, cage, faceplate) gets one more good year than the headline-CPO narrative implies. The NPO bridge generation is where the next twelve months of real engineering spending lands, and the supply chain has positioned itself accordingly: Innolight, USI, Marvell + Broadcom’s SerDes-IP socket, and TFC’s mass- production line in Suzhou are all set up for that bridge to be real.
The CPO disruption story isn’t wrong — it’s just two years further out than the slide-deck version, and on the way there it goes through the slowest packaging-yield curve the industry has tried to flatten in a decade.
Figures here are drawn from current supply-chain research (industry Q&A notes and sell-side reports through mid-2026) and stated as the thesis, not independently re-derived.
Cluster reading: What AI Hardware Is Running Out Of, What’s Cooling the AI Build-Out, Where Marvell Sits, Where Broadcom Sits.