Marvell’s entire AI story is a story about one specific layer of the optical supply chain — the chips between the photon and the data path — and how it owns, shares, or has been locked out of each box at that layer.
The simplest summary the rest of this piece backs up: Marvell owns the TIA layer almost outright, especially at 1.6T. It fights Broadcom for the DSP market and is currently losing the non-Nvidia tranche of it. It co-supplies the white-box switch silicon CSPs use to dodge Nvidia. It is a co-architect of the next-gen NPO route. And it is conspicuously absent from two of the highest-profile AI optical builds — Google’s 2.4T coherent program and the Nvidia–TSMC 3.2T CPO main line. Walking through each:
Companion pieces: What’s Cooling the AI Build-Out (the cage layer above this one) and What AI Hardware Is Running Out Of (the broader scarcity map).
What a TIA is, in one paragraph
A TIA — transimpedance amplifier — is a small electrical chip sitting between two larger ones inside the receive path of an optical module. The fiber drops light onto a PD (photodetector); the PD turns that light into a tiny current measured in microamps, way too weak for anything downstream to read. The TIA amplifies that current and converts it to a voltage signal that the DSP (digital signal processor) can decode. PD → TIA → DSP. The TIA is the amplifier between the photon and the brain.
That position — small, deeply embedded, hard to qualify a second source for — is why winning the TIA socket is sticky. And it is the socket Marvell has won.
The TIA monopoly, by speed and by fiber type
- 800G single-mode TIA: Marvell holds about 80% share; Semtech the remaining ~20%.
- 800G multi-mode TIA: Macom holds about 50%; Marvell and Semtech split the other half.
- 1.6T TIA (current generation): Marvell is the only company in volume production today. Macom and Semtech are still in sampling/qualification; their volume ramp is expected 1H 2027 at the earliest.
Two observations land hard out of that table. First, almost all of the 800G TIA growth is single-mode — which is exactly where Marvell is 4× the size of its nearest competitor. The incremental dollar in 800G TIA goes to Marvell. Second, the 1.6T cliff has currently turned into a year-plus lead: every 1.6T module that ships in 2026 ships with a Marvell TIA, by default. That’s the strongest single competitive position the company has in the entire AI build-out.
The DSP slugfest with Broadcom
One step down the receive path is the high-speed DSP, the brain of the module: it does the equalisation, the FEC (forward error correction), the data conversion, the framing — everything the TIA hands it. At 800G and 1.6T, the DSP is a leading-edge silicon part, and the market for it is a two-firm contest.
Marvell and Broadcom are the two giants. The split is not even. In the pluggable optical-module DSP market outside the Nvidia ecosystem (i.e. everywhere else — CSP-spec switches, white-box transceivers, the long tail), Broadcom holds something like ~90%. Marvell is the credible challenger but is materially smaller in this slice.
Both firms fight the same upstream bottleneck. The latest-generation DSPs (1.6T-class, leading-edge nodes) are essentially TSMC 3 nm parts. Marvell and Broadcom are both squeezing into the same overbooked 3 nm capacity, and that capacity — not engineering — is what gates how many 1.6T DSPs each can ship in 2026 and 2027. The fight isn’t design; it’s allocation.
White-box switches — where Marvell and Broadcom both win
Two competing camps are shipping the next-generation switching gear that will sit at the heart of CPO-class racks.
- Camp 1 — Nvidia. Closed, vertically integrated, software-plus-hardware bundle. CSPs cannot customise it.
- Camp 2 — Broadcom and Marvell. Sell chips (switch silicon plus core IP) to hyperscalers (Google, Amazon, Microsoft), which then build heavily customised “white-box” switches via JDM (joint-design manufacturing) and ODM (original-design manufacturing) partners.
The mental model: a white-box switch is a bare-metal PC and Marvell/Broadcom are the CPU. The CSP picks the box vendor, the OS, the cabling, the cooling — but the switch silicon underneath has two credible suppliers, and Marvell is one of them. Whichever way the CSPs jump within Camp 2, the switch-chip socket is jointly defended. That’s a structurally stickier position than the DSP fight upstream of it.
Where Marvell is absent
Two named programs do not ship Marvell silicon. They’re the two highest-profile builds in AI optics over the next eighteen months.
Google’s 2.4T coherent optical module. A scale-across program (data-centre-to-data-centre, coherent modulation) Google is building for its next-generation footprint. The core DSP in this program is Google’s own — built by an in-house team assembled out of former Inphi engineers. Marvell is not the DSP supplier. The standard read is “not ruled out as a second source later,” which translates to: today, Marvell isn’t in.
The Nvidia–TSMC 3.2T CPO main line. Nvidia is jointly developing its next-generation 3.2T CPO solution directly with TSMC. The reference design’s most-integrated layers — the optical-engine package on the substrate — are controlled by Nvidia and TSMC. Third-party module specialists, Marvell included, have essentially no direct seat at this layer of the main line. That doesn’t kill them in CPO broadly — the rest of the ecosystem (camp 2 above) is the alternative — but it does mean the highest-density Nvidia CPO box is one where Marvell’s native sockets (TIA, DSP) are absent or absorbed into the package.
NPO — Marvell as a co-architect
NPO (near-packaged optics) is the practical, near-term architecture sitting between today’s pluggable modules and tomorrow’s fully co-packaged CPO. The optical engine moves closer to the switch ASIC but doesn’t fully integrate onto its substrate. It’s the route most hyperscalers are betting on for the bridge generation.
NPO’s architecture is DSP-less at the optical engine. Signal recovery and equalisation get done instead by SerDes (serialiser / deserialiser) blocks paired with enhanced drivers and TIAs. The dominant SerDes-IP suppliers in the industry are Marvell and Broadcom. So the NPO route, even though it removes the DSP socket Marvell was contesting, hands Marvell a different, more deeply-embedded socket — the SerDes IP underneath the optical engine.
Among overseas players (i.e. excluding Alibaba, which is the most aggressive Chinese mover on NPO), Marvell and Amazon are the two leading the NPO push. That positions Marvell on the right side of the architecture transition even if DSP-less designs win the next generation.
The shape
Stacked together, the Marvell map looks like this:
- Strengths: the 1.6T TIA monopoly, the 80%-share of 800G single-mode TIA, and the SerDes-IP socket underneath NPO.
- Live fights: the DSP market against Broadcom (with Broadcom currently dominant in non-Nvidia at ~90%) and the joint scramble for TSMC 3 nm capacity that gates both sides.
- Conspicuous absences: Google’s 2.4T coherent (Google’s in-house DSP) and the Nvidia–TSMC 3.2T CPO main line.
The one-line read on Marvell’s AI position: technology lead in TIA, structural pressure in DSP, co-architect in NPO. The TIA monopoly buys time; the DSP fight is what gets resolved next; the NPO architecture decides whether the SerDes-IP socket replaces what the DSP socket used to be.
Figures here are drawn from current supply-chain research (industry Q&A notes and sell-side reports through mid-2026) and stated as the thesis, not independently re-derived.
Adjacent reading: What’s Cooling the AI Build-Out (the cage layer above this one); What AI Hardware Is Running Out Of (broader scarcity map — including the 200G EML cliff Marvell’s TIA rides on); Why Bet on Nokia (the DCI layer Marvell’s coherent DSP would have served).