Headline version: the optical engine moves onto the same substrate as the switch ASIC; the pluggable module disappears. Correct, and useless for understanding why CPO keeps slipping. The real story is a manufacturing problem.
↓what’s in the package
six steps · TSMC + NVIDIA · 2026 yield ~75%
build-up film
~10% die here
face-to-face bond
tol 0.5–0.6 µm
90–95%
The optical engine is a stack of three layers. The PIC (photonic integrated circuit) emits, modulates and receives light — silicon photonics on a 65 nm process. Bonded to it: the EIC (electronic integrated circuit) at 6 nm or lower.
to-face. one for
light, one for
electrons.
The FAU (fibre-array unit) holds the fibre that couples to the PIC’s waveguides. CPO needs a 3-D design with channel pitch under 100 µm and sub-micron alignment. The CW (continuous-wave) laser sits outside the package at ≥ 300 mW per channel.
must line up
to under a micron.
⚡the six steps
1. PIC + EIC hybrid bonding. Wafer-level, face-to-face, sub-micron. The hardest step in the flow — ~10% of CPO units die here. Specialist bonder equipment runs $1–2 M with 5–7 month lead times.
sink. 1 in 10
dies right here.
2. Wafer dicing. Cut into individual OE die. Standard process. 3. Substrate flip-chip. Mount the OE die onto an ABF (Ajinomoto Build-up Film) substrate. Standard advanced-packaging plumbing.
yield is fine.
4. FAU active coupling. Second-biggest yield sink. Tolerance is 0.5–0.6 µm. Not a robot problem — needs experienced engineers, training cycle over six months. Full automation line: ¥10 M+ ($1.4M+).
robots. 6-month
training cycle.
5. System integration. Co-mount the OE module with the switch ASIC on a single carrier — projected to reach 150 mm × 200 mm, bigger than a phone. Done by ASE (and other OSATs).
CPO module.
6. External CW source attachment. Off-package laser plugs in via fibre. TSMC went to a blind-mate design — skips the slow active alignment, saves cycle time and yield risk at end-of-line.
no alignment.
⌖why yield is stuck at 75%
DNA mismatch. Semiconductor (sub-nanometre, defect-driven) and optics (alignment-driven, hand-tuned) have never shared a process line at this scale. Tolerances compound at the meeting points.
neither used to
the other’s
tolerances.
Thermal. The switch ASIC dissipates kilowatts. The optical engine sits millimetres away. Light walks off-channel with the smallest temperature drift. Current cold plates weren’t designed for this geometry.
sitting next to
kilowatt chips.
Test floor. Nvidia mandates 100% end-to-end test on every wafer. A wafer with 200–300 channels takes over twenty hours to fully test — throughput cap, not yield cap.
wafer. the test
floor is the
slowest step.
※the closed NVIDIA – TSMC alliance
The reference CPO main line is jointly owned by NVIDIA and TSMC, and the line is not open. Broadcom, AMD and the large module makers are second-tier customers of TSMC’s packaging slots.
in the alliance
or you wait.
CSP resistance is the flip side. Hyperscalers don’t want a supplier list of one, can’t scale CPO one port at a time, and don’t want to lock in the whole NVIDIA-TSMC stack underneath it. Their hedge: wait for NPO, keep pluggables.
↓unit economics
CPO switch sticker: ¥150,000 versus electrical switch + pluggable stack at ¥80,000. Full-year 2026 CPO switch shipments: ~15,000 units at the 75% yield. Nowhere near volume-economic.
few hundred
million. TSMC
slow-walks for
a reason.
→orders and project status
NVIDIA. Ordered 20,000 PIC wafers from TSMC in Feb 2026. First CPO switches ship Aug / Sep 2026. Put $2 B equity into Coherent and a multi-billion buy commitment with Lumentum. Original Q2–Q3 ramp is now Q4.
supply chain.
still slipped
a quarter.
Broadcom. Behind on every dimension. Approach is 2.5-D packaging (vs TSMC’s 3-D). Volume guided 2H 2027 → 2028 — the same window in which its own EML + DSP business has the most to lose.
the catch-22.
TFC Communication (天孚通信). NVIDIA’s core OE component supplier — FAU, microlens, ferrules. Delivered a first 7,200-piece FAU order (demo / verification only). Eight CPO lines in Suzhou; mass production Q3–Q4 2026.
supplier. real
production this
year.
Foxconn Industrial Internet (工业富联). NVIDIA’s exclusive CPO switch assembler. Small-batch testing alongside Rubin Super Pod. Production Q4 2026. FY 2027 target 25,000 units; realistic ~10,000+.
Nvidia ships
CPO switches
through.
Innolight (中际旭创). Submitted an NPO solution — not CPO — to NVIDIA. Running CPO pre-research with JCET on the side. Betting on the bridge. USI / Universal Scientific (环旭电子). Same bridge-tier bet, NPO samples mid-2026.
betting NPO.
Coherent (II-VI). Large CPO order from a top AI customer (effectively NVIDIA-side). CW source sample shipments running. Its diamond-particle SiC ceramic thermal material doesn’t care which CPO route wins.
and the cooling
material — both
route-neutral.
↓one-line read
Real volume on CPO is a 2027–2029 story. 2026 stays inside five digits. The pluggable empire (EML, DSP, cage) gets one more good year than the headline narrative implies. NPO is where the next twelve months of real engineering spend lands.