The PCB Stack Inside an AI Rack

Five PCBs sit inside a current-generation AI rack. The fight to supply each is a different fight, and the share map is moving fast enough that two consecutive Rubin generations could ship with completely different vendor lists. This piece walks what the five boards are, why they exist at all, the three technical barriers that decide who gets to make them, and where the live battle lines sit between mainland-Chinese and Taiwanese suppliers.

Cluster: this is the PCB layer in the same AI-hardware build-out covered by What AI Hardware Is Running Out Of (HVLP4 copper foil + Low-DK glass cloth, the inputs to these boards), What’s Cooling the AI Build-Out (the cages stacked above them), and How CPO Actually Gets Built (the 576-rack architecture that makes the mid plane and the orthogonal backplane necessary in the first place). If the vocabulary is familiar but the picture is not, start with the five-minute basics review (cache / memory, PCB factory walk, GPU).

The five boards inside the rack

Reading top-down, you encounter each board at a different layer of the rack’s architecture.

• HDI compute board. The board that carries the GPUs. HDI — high-density interconnect — uses microvias, fine line / space geometry (today around 50 µm width and pitch, future targets 10 µm), and multiple lamination passes to pack interconnect density. Current production on GB200 / GB300 uses fifth-order 22-layer HDI: five HDI lamination passes in a 22-conductor-layer stack. The next-generation Rubin platform moves it to seventh-order 26-layer HDI. Per-board value runs from ¥25,000 (smaller OAM variant) to ¥40,000 (full-size).
• Switch board. Routes data between compute boards. Built on multi-high-layer through-hole stack, mainstream today is 32-layer, current consensus material is M9. The difficulty is not the design but plating uniformity and signal integrity across the very large board format. Suppliers today: Victory Giant, Wus Printed Circuit, TTM.
• Mid plane. A new component for the 576-rack generation. Connects compute board to CPX board inside a single drawer, replacing the copper cables that were the GB200 / GB300 system. Built as a 44-layer small orthogonal backplane — two 22-layer PCBs copper-sintered together. Material: M9 + Q-cloth (quartz glass cloth) + fourth-generation copper foil. A single 576-rack cabinet uses 18 mid planes, one per compute drawer.
• Orthogonal backplane. The rack-level skeleton — a door-sized PCB connecting all compute drawers and switch drawers, forming the cabinet’s data exchange bus. Stacks reach 78 to 104 layers, built by copper-sintering multiple 22-layer or 16-layer sub-PCBs into one giant board. Difficulty is purely process yield: lamination of dozens of layers in large format with high-precision back-drill and plating, where defects compound geometrically.
• Substrate-like PCB. Not in 2026 racks. The future board sitting between today’s HDI and an IC substrate — line widths come down from 50 µm to roughly 10 µm, almost at chip-package density. This is the threshold that decides Rubin-generation supply share. More on this below.

Why the mid plane and backplane exist

The current Blackwell generation racks — GB200 and GB300 — connect compute boards to switch boards through over 5,000 copper cables per rack. Assembling that cable bundle is the named reason GB200 deliveries slipped: the manual operation is slow, error-prone, and produces a fault distribution that scales with cable count.

The 576-rack architecture that replaces it for Rubin and Rubin Ultra drops the cables for an orthogonal backplane structure — instead of point-to-point cables, every drawer plugs into the same rigid PCB skeleton. The mid plane is the drawer-level expression of that same architectural shift: inside each compute drawer, what used to be cables connecting compute board to CPX board becomes one 44-layer orthogonal mid plane.

The point isn’t per-board performance — it’s system-level reliability and assembly throughput. The mid plane / backplane stack replaces 5,000 manual cable terminations with a handful of standardised connectors, raising automation rate and throughput by something close to an order of magnitude. That’s the actual case for the architectural shift.

Barrier 1 — High-end HDI and substrate-like PCB

The technical mark that already separates today’s leaders from today’s incumbents is yield on fifth-order 22-layer HDI. Taiwan’s Unimicron, the historical leader, runs this product at around 80% yield. Mainland China’s Victory Giant Technology runs it close to 90%. The reason isn’t novel chemistry or proprietary IP — it’s factory age. Unimicron’s line was built in 2001–2002, with the automation, environmental control, and process telemetry of that era. Victory Giant’s line is a 2024-onward greenfield with full-process automation. Factory generation has become a real competitive variable in PCB.

The next mark is much harder. Substrate-like PCB (sometimes “SLP”) sits between today’s HDI and the ABF-based IC substrate stack used in chip packaging. Line widths and spaces come down from 50 µm to about 10 µm; tolerance budgets shrink toward chip-packaging discipline; and crucially, the entire production line has to run as a full-process clean room — not the “clean at the critical steps” pattern conventional HDI uses. Retrofitting an existing HDI plant doesn’t reach the required defect density. Substrate-like PCB requires a new plant.

That makes substrate-like PCB the seventh-order 26-layer HDI’s real prerequisite and the first board that will appear in Rubin-generation NVIDIA boxes. Two mainland companies enter the race with credible head starts:

• Avary (鹏鼎). Has years of substrate-like PCB experience from flagship-iPhone production. The know-how transfers directly: same line-width regime, same clean-room discipline, same metrology stack. Avary’s disadvantage is that it has historically been a consumer-electronics PCB house; making that pivot at AI-server volumes is the open question.
• Victory Giant. Has the current HDI lead but has to build the new SLP-capable plant. Its track record on AI-server PCB execution speed (the “Q4 certification → order → production” cycle on the current generation) is the case for it doing it again. Capex is large; financing schedule is what gates it.

Unimicron, by contrast, has visibly tilted strategic priority toward ABF substrate — the chip-package side of the packaging stack — and away from high-end HDI. That choice may turn out fine for its substrate business, but it leaves the AI-server PCB front under-resourced exactly as the substrate-like-PCB mark is being defined.

Barrier 2 — M9 / Q-cloth and PTFE: when materials retire equipment

Two material transitions are also functioning as competitive resets.

Q-cloth (quartz glass cloth), the reinforcing fibre in top-grade Low-DK / M9 laminate, is so hard that conventional mechanical drilling can’t process it economically — drill bits wear in single-board cycles and hole-wall quality is poor. That retires a generation of drilling equipment. Han’s Laser brought a laser-drill platform compatible with M9 + Q-cloth and is shipping it to Victory Giant; industry consensus has domestic Chinese laser-drill share heading past 60% on the M9 product. This is the textbook case of a material transition becoming a mainland-equipment-vendor opening.

PTFE (polytetrafluoroethylene — Teflon-class material) is at the other extreme: very soft, chemically nearly inert. It’s wanted for ultra-low-loss radio-frequency-class boards, but processing it requires bespoke chemistry. NVIDIA initially courted multiple vendors; only Avary and JWG (Joyfay / Jingwang) stayed in the R&D loop — everyone else withdrew. Avary has since taken over the PTFE business previously held by Senke and submitted samples to NVIDIA. This is the kind of small, quiet supplier reshuffle that compounds into 2028 share lists.

Barrier 3 — Copper sintering: process yield at scale

Mid plane and orthogonal backplane both rely on copper sintering — bonding multiple multi-layer sub-PCBs into a single laminated stack at high precision. The problem is not chemistry or design. It’s manufacturing physics: large, thick boards have to be heated and pressed uniformly without delamination, blistering, or sub-millimetre dimensional drift. Sintering precision drops geometrically with board size and layer count.

No one has years of head start here — copper-sintered orthogonal backplane in AI server form factors is essentially industry-first. The competitive variable is execution speed: who can run their first defect-quantified yield curve up the slope fastest. Mainland China’s pattern has been to compress the certification → first-order → production cycle into a single quarter; Taiwanese counterparts move on a half-to-full-year cycle. That speed differential, repeated over two generations, is the actual mechanism of share migration.

The supplier map by board

Where each name stands today.

• HDI compute board (NVIDIA GB200 / GB300). Victory Giant > 70% share, Unimicron the remainder. The 70/30 split is the headline data point of mainland overtake.
• Switch board. Victory Giant, Wus Printed Circuit, TTM. Multi-supplier today; M9 transition is reshuffling.
• Mid plane (NVIDIA 576). Victory Giant — high probability lead. Wus and others still in qualification.
• Orthogonal backplane. Multi-vendor qualification in progress: Victory Giant (first to pass sample), Unimicron, Jingwang, Avary, Wus.
• Substrate-like PCB (Rubin generation). Avary on early substrate experience; Victory Giant on factory-build commitment. Open race.

The other customer — Google's TPU build-out

Google’s 2026 guidance walked its TPU shipment forecast from 2.5–3 million chips up to ~4 million chips. At roughly $9,000 per TPU and 64 chips per rack (~ $1.9 M per rack), the implied chip line alone is in the tens of billions of dollars; the pull-through into PCB, optical, and cooling is a multi-tens-of-billion supply-chain expansion. This is the “Google $10 B order” headline in its actual form — a forecast revision that broadcasts demand downstream.

Two things change about the PCB market in Google’s case relative to NVIDIA’s.

First, Google TPU boards use multi-high-layer PCB, not HDI. The architectural reason: NVIDIA GPU SerDes runs at a signal regime where HDI’s low-loss interconnect is the right trade-off; the TPU’s ASIC has higher link-level signal loss, which is compensated by a more conservative, higher-layer through-hole stack rather than denser HDI routing. The board is 22–24 layers on M8 / M9 material. Supplier map: ISU, Wus Printed Circuit, ChaoYing (with Foxconn-affiliated ChaoYing the most volume-aggressive new entrant).

Second, Victory Giant is trying to enter Google’s supply chain, not yet in. The certification cycle for new vendors at Google runs around six months, and the move slow. Its case for entry is the NVIDIA HDI track record (a credible 22-layer high-yield manufacturer), not its existing relationship at Google.

The other hyperscalers fill in the picture: Meta consolidated on Wus Printed Circuit for its custom-accelerator PCB. Amazon uses SCI Electronics and Kinwong on Trainium / Inferentia boards. The CSP side of the PCB market is less concentrated than the NVIDIA side, and more of it is going to mainland Chinese vendors with each new accelerator generation.

The shape

1. Mainland Chinese PCB houses already lead on the current-generation NVIDIA stack. Victory Giant’s >70% share of GB200 / GB300 HDI compute boards, at ~90% yield against Unimicron’s ~80%, isn’t a future prediction — it’s 2026.
2. The next mark is substrate-like PCB. It needs a new full-process clean plant, not a retrofit. The credible candidates are Avary (Apple-side substrate-like experience) and Victory Giant (factory-build commitment). Unimicron has visibly shifted strategic priority toward ABF substrate instead.
3. Materials and equipment are reshuffling at the same time. M9 + Q-cloth retires an entire generation of mechanical drilling and opens the door for Han’s Laser. PTFE consolidates onto Avary and Jingwang. Copper sintering for mid plane and backplane is an industry-first race where execution speed dominates.
4. Google’s TPU buildout is a separate fight — multi-high-layer not HDI, ISU and Wus already incumbent, Victory Giant queueing for certification.

Net: the PCB layer of the AI build-out has the cleanest, most-measurable case for a structural mainland-China share gain in the entire AI hardware stack. The variable to watch over the next twelve months is which mainland house breaks ground on the first credible substrate-like PCB plant — that plant’s commissioning date is when the Rubin-generation share map is decided.

Figures here are drawn from current supply-chain research (industry Q&A notes and sell-side reports through mid-2026) and stated as the thesis, not independently re-derived.

Cluster reading: What AI Hardware Is Running Out Of, What’s Cooling the AI Build-Out, Where Marvell Sits, Where Broadcom Sits, How CPO Actually Gets Built.