Inside Huawei, the Ascend 950 has a codename: David. Across the table is Goliath.
That codename gives away how Huawei thinks about this — and where the real tension sits. David's stone takes down a giant, but only if the giant stands still long enough to be aimed at. NVIDIA does not stand still: it ships a new architecture every year, and never stops sharpening the one already in the field. Huawei has proven it can throw a precision stone on Day 0. Whether it can hit a Goliath that is still running is another question.
But staring at the stone is staring at the wrong thing. Most of the noise around Atlas 950 fixates on the chip — one process generation behind, a third of NVIDIA's per-card throughput — and draws a conclusion. In a real datacenter, the silicon is less than 20% of the cost. The other 80% is interconnect, cooling, power, and the engineering that organizes ten thousand cards into one machine. The chip is the engine. This fight is about the chassis, the gearbox, and the entire drivetrain.
So start with the technical heart.
Unified memory — collapsing the cluster into a single machine
The classic pain of a ten-thousand-card cluster is not compute. It is compute sitting idle. There are plenty of cards, but each one can only address its own slice of HBM — High Bandwidth Memory, the on-package memory that feeds each accelerator. Talking to another card means copying, syncing, waiting. Add tensor parallelism and MoE (Mixture of Experts — the routing trick that lets today's biggest models activate only a slice of their parameters per token) and communication overhead eats most of the useful throughput. The cards spin. The work does not move.
Unified memory addressing flips this from a cluster problem into a single-machine problem. A fully-loaded Atlas 950 SuperPoD packs 8,192 Ascend NPUs (Neural Processing Units — Huawei's GPU equivalent), stitched together by UnifiedBus all-optical fabric into a shared memory pool of 1,152 TB, where every card lives in one address space. A card reading another card's HBM looks identical to reading its own. The physical boundary stays; the logical boundary disappears.
The physical layer holds it together with three hard numbers. Bandwidth: UB-Mesh's recursive direct topology pushes total fabric bandwidth to 16.3 PB/s — 62× the industry average. That is the foundation that actually kills the data-shipping bottleneck. Latency: round-trip time drops from 7 microseconds to 3. For gradient-sync on trillion-parameter models and KV-cache (the conversation memory inference engines reuse across tokens) shuttled card-to-card, every microsecond shaved is effective compute gained.
That is what "compensating for the single card with the swarm" actually means. Do not fight 3 nm or 2 nm on one die. Take address-space unification plus all-optical interconnect, and erase the per-card disadvantage at the system layer.
"6.7×" is true — with a caveat
Huawei's official comparison: against NVIDIA's same-window NVL144, the Atlas 950 has 56.8× the card count, 6.7× total compute, 15× the memory, and 62× the interconnect bandwidth.
The numbers are not fake. There is a caveat worth saying out loud. The 6.7× is Huawei's ~160-cabinet, 8,192-card full-rack array compared to NVIDIA's single 144-card cabinet. NVIDIA's SuperPods can also scale to hundreds of cabinets. A hundred people on a scale outweigh an elephant — that does not make one person heavier than an elephant.
The honest version: per-card behind. Like-for-like, not necessarily ahead. But on the largest single coherent SuperPoD one vendor can organize — the dimension trillion- and ten-trillion-parameter training is most sensitive to — Huawei is genuinely first. Said this way, the claim is both sharp and defensible.
Software — the narrative flipped half-way in 2026
CANN is to CUDA what MindSpore is to PyTorch. In August 2025 Huawei open-sourced CANN, trying to crack the moat NVIDIA spent eighteen years building. Every bear case landed on the same line: the ecosystem gap is too wide, migration is too expensive, and the open-source community is probably 100% Huawei employees committing to themselves.
That line took a hit in 2026 with one data point. When DeepSeek V4 dropped, Ascend was a launch platform with first-class Day 0 support. Part of DeepSeek's official API runs on Huawei from day one. More striking: only two software stacks on the planet had Day 0 support for DeepSeek V4 — CUDA, and CANN. AMD's ROCm did not get there on launch day. A year earlier, when V3 / R1 launched, that list had one entry.
The hardware lineup is not a prop, either. The 950 splits into 950PR (Prefill / recommendation, cheaper, throughput-tuned) and 950DT (Decode / training, higher-bandwidth, higher-performance) — same die, dual-die UMA architecture. Independent matrix cores (AIC) and vector cores (AIV) run in dual-master mode. On-chip AI CPU. A dedicated CCU communication engine that echoes TPU and Trainium's purpose-built designs. Plus MC² (compute-communication fused operators), introduced back in 2024. The ecosystem gap still exists. The speed at which it is closing has outpaced its 2025 pricing.
The real ceiling — HBM
If the story stopped here it would be a brochure.
The sharpest bear case does not come from the system layer. Even SemiAnalysis concedes that Huawei's chip is a process generation behind, but its scale-up system architecture is a generation ahead of NVIDIA's and AMD's shipping products — and that the system matters more than the microarchitecture. The doubt collapses onto one specific atom: HBM.
The system advantage is, fundamentally, a memory advantage. The whole Atlas 950 story — the 1,152 TB shared pool, the 15× memory capacity vs NVL144 — sits on a mountain of HBM. The previous-generation CM384 already had 3.6× the aggregate memory and 2.1× the bandwidth of GB200 NVL72. More cards means a bigger pool means more HBM, linearly. The "swarm compensates for the single card" strategy trades a dependency on cutting-edge logic process for a dependency on HBM supply. It routes around the lithography machines. It cannot route around the memory.
China itself knows where the choke is. No need to guess Huawei's anxiety — look at what it asks for at the negotiating table. In US–China talks Beijing has specifically asked for looser HBM controls — not for looser TSMC capacity, not for looser EUV equipment. The detail of what gets asked for, and what does not, is its own signal. The bottleneck is not logic process. It is memory.
The stockpile was smuggled, and it is draining. The Ascend NPUs running today mostly run on memory from a one-off scramble. Samsung shipped 11.4 million HBM stacks specifically to China — 7 million of them inside the one-month window between when the December 2024 export restriction was announced and when it took effect. (The restriction had been pre-announced for months, which acted as a buffer.) After the restriction took effect, a smuggling channel kept things going for a while: companies like CoAsia and Faraday shipped HBM-bearing "non-functional" chips into China — technically compliant as long as the package did not exceed the FLOPS red line — then de-soldered the HBM domestically. Packages used low-temperature solder joints to make decap easier. That channel was reportedly shut down after public exposure. Across all routes, ~13 million HBM stacks total, enough to package about 1.6 million Ascend 910Cs. Foreign-sourced HBM is expected to run out by year-end, after which production hits the wall.
It is not the logic that cannot be made — it is that there is no memory to pair it with. The most counterintuitive and most damaging point: capacity is not gated by lithography, it is gated by memory. SMIC can fab about 1 million 910C dies and ~500,000 910B dies this year — and a lot of those dies will never become finished products because there is no HBM to attach. SemiAnalysis lays out the math cleanly: if every advanced-logic die could be paired with HBM, Huawei's Ascend production next year would jump from 300,000 to over 5 million units. That 16× gap — 300K vs 5M — is entirely bound by HBM. Lithography and SMIC yield are not the blocker. The alternative — falling back to slower GDDR or LPDDR memory — cannot sustain frontier-model training that depends on modern reinforcement learning, and cannot sustain large-scale inference deployment either.
Domestic HBM cannot fill the gap. CXMT is catching up fast — poaching from Samsung, SK Hynix, and Micron, already shipping DDR5, only a year or two behind the leaders. HBM is a different problem. SemiAnalysis estimates CXMT can produce ~2 million HBM stacks next year — enough for 250,000 to 300,000 Ascend 910Cs. Yield ramps and line conversions take time. The money is not the problem: China's Big Fund Phase 3 injected $2 billion into CXMT in May 2024. But money does not buy years.
The real bet
Three things, side by side.
- System engineering — the result is in. Huawei won.
- Software ecosystem catch-up — the evidence is documented. Day 0 DeepSeek V4 on Ascend is exhibit A.
Neither of these is a variable anymore.
The one asymmetric risk sits on a single input Huawei does not control: an HBM stack, one at a time, smuggled in from Korea, eventually burned through. UnifiedBus could be ten times better; unified addressing could be twice as elegant. None of that decides how many 8,192-card SuperPods Huawei ships in 2026 and 2027. Two curves decide that — CXMT's yield climb, and how long the stockpile holds. The system architecture is "can it be designed." HBM is "can it be built." The first Huawei won. The second is locked in someone else's hands.
Back to the codename. David's stone aimed true. But this time the giant is not standing still, and David's ammunition — not his aim — is dropping one stack at a time.
The bet is not on UnifiedBus. The bet is on the not-yet-ramped CXMT line in Hefei, and on the day the stockpile hits zero — and which one gets there first.
Related technical repos
- CANN open-source community — gitcode.com/cann/community (includes the DeepSeek V4 Ascend Day-0 inference optimization slides)
- cann-recipes-infer — gitcode.com/cann/cann-recipes-infer (Ascend DeepSeek V4 inference recipe; MTP / decode-step timing implementation)
- SemiAnalysis InferenceX — github.com/SemiAnalysisAI/InferenceX (cross-chip Day-0 inference performance tracker, including the 950DT)
- SGLang DeepSeek V4 support — github.com/sgl-project/sglang/pull/23600; performance-optimization tracker: issues/23666
- vLLM DeepSeek V4 roadmap — github.com/vllm-project/vllm/issues/40902
Source note
Data and judgements draw primarily from three SemiAnalysis reports plus Huawei's own disclosures:
- Huawei AI CloudMatrix 384 — China's Answer to Nvidia GB200 NVL72, Dylan Patel et al., 2025-04 (system architecture, power, all-optical interconnect, TSMC / HBM external dependencies).
- Huawei Ascend Production Ramp: Die Banks, TSMC Continued Production, HBM Is The Bottleneck, 2025-09 (production volumes, die-bank accounting, the Samsung HBM scramble, CXMT capacity estimates).
- DeepSeek V4 1.6T Day 0 to Day 43 Performance Over Time, 2026-06 (950PR / 950DT architecture, CANN Day-0 inference, the David codename).
SuperPoD specs and the comparison multiples (8,192 cards / 1,152 TB / 16.3 PB/s / 6.7×, 56.8×, 15×, 62×) come from Xu Zhijun's keynote at Huawei Connect 2025 and the overseas debut at MWC Barcelona 2026.